Japanese Patent Application Laid-Open Publication No. 2014-229623 (Patent Document 1) discloses a technique in which an electrode pad formed on a surface of a semiconductor chip and a lead electrode of a wiring board are connected via a Cu pillar.
International Publication No. 00/44043 (Patent Document 2) discloses a technique in which bonding pads arranged in a peripheral portion of a semiconductor chip and bump electrodes arranged in an entire chip surface area are connected by rearrangement wiring. It further discloses a chip size package in which a semiconductor chip having bump electrodes arranged on a surface thereof is connected onto a mounting board by face-down bonding, and a gap between the semiconductor chip and the mounting board is filled with underfilling resin.